K4T51163QG-HCE6

DDR2 SDRAM, 32Mx16, 84 FBG

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PartNumber:: K4T51163QG-HCE6

Brand:: Samsung semiconductor - SAMSUNG | Pack: BGA | D/C: 10+

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Products Upload time: 2011-04-19

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Part Number:K4T51163QG-HCE6
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Product Summary

The K4T51163QG-HCE6 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x4banks or 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks device. This synchronous device achieves high speed doubledata-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency -1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.

Parametrics

Absolute maximum DC ratings: (1)VDD, Voltage on VDD pin relative to VSS: - 1.0 V ~ 2.3 V ; (2)VDDQ, Voltage on VDDQ pin relative to VSS: - 0.5 V ~ 2.3 V ; (3)VDDL, Voltage on VDDL pin relative to VSS: - 0.5 V ~ 2.3 V ; (4)VIN, VOUT Voltage on any pin relative to VSS: - 0.5 V ~ 2.3 V ; (5)TSTG, Storage Temperature: -55 to +100℃.

Features

Features: (1)JEDEC standard 1.8V±0.1V Power Supply; (2)VDDQ = 1.8V±0.1V; (3)200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin; (4)4 Banks; (5)Posted CAS; (6)Programmable CAS Latency: 3, 4, 5, 6; (7)Programmable Additive Latency: 0, 1 , 2 , 3, 4 , 5; (8)Write Latency(WL) = Read Latency(RL) -1; (9)Burst Length: 4 , 8(Interleave/nibble sequential); (10)Programmable Sequential / Interleave Burst Mode; (11)Bi-directional Differential Data-Strobe (Single-ended datastrobe is an optional feature); (12)Off-Chip Driver(OCD) Impedance Adjustment; (13)On Die Termination; (14)Special Function Support: PASR(Partial Array Self Refresh); 50ohm ODT; High Temperature Self-Refresh rate enable; (15)Average Refresh Period 7.8us at lower than TCASE 85℃, 3.9us at 85℃ < TCASE ≤ 95 ℃; (16)All of products are Lead-free, Halogen-free, and RoHS compliant.